1. Field of the Invention
The present invention is directed to the design of integrated circuits. More specifically, but without limitation thereto, the present invention is directed to computer algorithms for predicting cell delays in integrated circuit designs.
2. Description of Related Art
To verify the performance of an integrated circuit design, the cell delays in each net of the integrated circuit design are typically estimated during the early design stages and also during floorplanning and routing. A timing closure is performed for the estimated cell delays to detect improper timing relationships among the cells in the integrated circuit design. Corrections are then made to the integrated circuit design, and the timing closure is repeated until all the timing errors have been corrected.